Complete 8086 Instruction Set & Opcode Reference Table
A rigorous, developer-focused reference dictionary for the Intel 8086 Instruction Set Architecture (ISA). Map out machine code opcodes, operational hex data configurations, register byte allocations, and execution flag mutations inside the Emu8086 simulator workspace.
1. Data Transfer Group Instructions
Mechanics for moving bit patterns between registers, memory spaces, and I/O peripheral subsystems.
Data transfer operations are non-destructive to the source operand and, as a fundamental rule of the Intel 8086 architectural design, do not modify any conditional status flags inside the FLAGS register matrix (such as Zero, Carry, or Sign flags).
| Instruction | Syntax / Example | Functional Operation Description | Flags Affected |
|---|---|---|---|
| MOV | MOV DX, [BX] MOV AX, 1234h |
Copies raw data byte or word vectors from a source operand directly to a specified destination. Memory-to-memory moves are strictly prohibited. | None |
| PUSH | PUSH AX PUSH [SI] |
Decrements the Stack Pointer register (SP) by 2, then transfers a 16-bit word data block into the Stack Segment memory block targeted by SS:SP. | None |
| POP | POP BX POP DI |
Extracts the 16-bit word located at the top of the runtime memory stack, writes it to the destination operand, and increments SP by 2. | None |
| XCHG | XCHG AH, AL XCHG CX, [BP] |
Swaps the binary contents of two distinct operand locations. Segment registers cannot be passed as parameters to this operational instruction. | None |
| LEA | LEA BX, array LEA DX, [SI+2] |
Load Effective Address. Calculates the absolute 16-bit offset address of the source memory operand and moves it into the targeted destination register. | None |
2. Arithmetic Group Instructions
Mathematical operations executing binary calculations and mutating conditional system status flags.
Unlike data transfer commands, Intel 8086 arithmetic instructions process unsigned or two’s complement signed integer values, updating the status bit values inside the FLAGS register layout after every single execution clock cycle.
| Instruction | Syntax / Example | Functional Operation Description | Flags Affected |
|---|---|---|---|
| ADD | ADD AX, BX ADD [DI], 05h |
Adds the source operand to the destination operand and saves the cumulative value inside the designated destination. | OF, SF, ZF, AF, PF, CF |
| ADC | ADC DX, CX ADC AL, [SI] |
Add with Carry. Adds the source, destination, and the current value of the Carry Flag (CF) together. Used for multi-word mathematical chains. | OF, SF, ZF, AF, PF, CF |
| SUB | SUB AX, 1000h SUB CH, CL |
Subtracts the source operand value from the destination operand and stores the result in the destination operand profile. | OF, SF, ZF, AF, PF, CF |
| INC / DEC | INC SI DEC BYTE PTR [BX] |
Adds or subtracts exactly 1 from the targeted operand destination. Crucial: These commands never change the Carry Flag (CF). | OF, SF, ZF, AF, PF |
| CMP | CMP AX, 00h CMP DL, AL |
Compares operands by subtracting source from destination. The destination profile value remains completely unmodified. Only FLAGS shift to prepare for jump statements. | OF, SF, ZF, AF, PF, CF |
3. Logic & Bit Manipulation Group Instructions
Bitwise operational directives for mask filtering, status testing, and high-speed binary shifting.
Logical instructions in the Intel 8086 architecture process bit patterns at the atomic level. Most bitwise operations (AND, OR, XOR) automatically clear the CF and OF status flags to 0, while the SF, ZF, and PF flags are updated based on the resulting bit vector outcome.
| Instruction | Syntax / Example | Functional Operation Description | Flags Affected |
|---|---|---|---|
| AND / OR / XOR | AND AL, 0Fh XOR BX, BX |
Performs bitwise logic between operands. XOR reg, reg is a standard high-speed idiom inside the Emu8086 compiler to clear a register to zero. |
SF, ZF, PF (CF=0, OF=0) |
| TEST | TEST AL, 01h TEST BL, CL |
Executes a bitwise AND between operands to update conditional flags, but does not modify the destination operand. Essential for checking specific bit statuses. | SF, ZF, PF (CF=0, OF=0) |
| NOT | NOT AH NOT BYTE PTR [DI] |
Performs a One’s Complement operation by inverting every individual bit inside the operand. Notice: This instruction does not alter any flags. | None |
| SHL / SHR | SHL AX, 1 SHR DL, CL |
Shift Logical Left/Right. Shifts bits in the operand, filling empty slots with 0s. The last bit shifted out is moved into the Carry Flag (CF). | CF, OF, SF, ZF, PF |
| ROL / ROR | ROL BL, 1 ROR AX, CL |
Rotate Left/Right. Bits shifted out from one end are re-inserted into the opposite end. The Carry Flag (CF) also receives a copy of the rotated bit. | CF, OF |
4. Control Transfer & Branching Group Instructions
Instructions regulating loops, conditional logic conditional branching, and subroutine pipeline execution.
Control transfer instructions modify the execution stream by loading new memory offset target coordinates into the Instruction Pointer (IP) register (and occasionally the Code Segment (CS) register). They evaluate conditions without modifying data bits.
| Instruction | Syntax / Example | Functional Operation Description | Condition Trigger |
|---|---|---|---|
| JMP | JMP my_label | Unconditional Jump. Forces execution control to seamlessly migrate over to the memory location address bound to the targeted destination label point. | None (Always) |
| JZ / JE | JZ error_handler | Jump if Zero / Jump if Equal. Diverts the instruction pipeline if the execution of the preceding operation raised the Zero Flag (ZF = 1). | ZF = 1 |
| JNZ / JNE | JNZ repeat_loop | Jump if Not Zero / Jump if Not Equal. Standard branching loop execution protocol triggered exclusively when the Zero Flag remains unasserted (ZF = 0). | ZF = 0 |
| LOOP | LOOP array_scan | Decrements the CX register automatically by 1. If the updated evaluation bounds show CX != 0, the pipeline executes a jump target reset. |
CX != 0 |
| CALL / RET | CALL my_procedure RET |
CALL transfers control to a procedure after pushing the current IP onto the stack. RET pops the instruction coordinates back off to return cleanly. |
None |
5. Processor Control & Interrupt Group (INT 21h Matrix)
Standard software vector interrupts executed inside the Emu8086 subsystem to manage screen console output and execution termination.
The INT 21h soft interrupt instruction intercepts standard application flows to execute MS-DOS sub-system kernel functions. Prior to invoking the interrupt trigger, the target function code must be successfully written straight into the AH register.
| Interrupt | Function (AH) | Required Parameters | Resulting Execution Behavior |
|---|---|---|---|
| INT 21h | AH = 01h | None | Halts the microprocessor execution pipeline to wait for a console keyboard stroke. The matching ASCII character code is automatically returned in the AL register and echoed to the screen display. |
| INT 21h | AH = 02h | DL = ASCII Character | Outputs a singular text character vector onto the system command line interface terminal. The specific byte to render must reside inside the DL register container. |
| INT 21h | AH = 09h | DX = Offset Address | Prints a complete data text block string onto the emulator monitor screen. The string pointer array must be explicitly mapped to DS:DX and must terminate with a dollar sign character marker ($). |
| INT 21h | AH = 4Ch | AL = Return Code (usually 00h) | Terminates application execution streams cleanly. Flushes standard registers and safely transfers task coordination privileges back over to the parent operating system interface container. |
6. Architectural Foundation: Understanding Memory Addressing Modes
How the Intel 8086 microcode engine computes effective source and destination memory pointer targets.
To accurately parse and execute any operational code table row inside the Emu8086 emulator layout, you must master how operands find their targets. The Intel 8086 supports several native addressing variations divided into core conceptual groups:
💡 Immediate & Register Addressing Modes No Memory Access Clock Cycles
Data is stored directly inside the instruction stream bytes or inside physical CPU register blocks. Execution speeds are exceptionally fast.
MOV CX, DX ; Register Mode: Shifting bit vectors straight between data components
💡 Direct & Register Indirect Addressing Modes Computes Effective Address
Targets segment memory. Direct addressing uses a static numerical offset inside brackets. Indirect addressing uses structural pointer tracking registers (BX, BP, SI, DI) to dynamic handle memory calculations.
MOV DX, [BX] ; Register Indirect Mode: Uses the target offset address stored dynamically inside BX
💡 Based Indexed with Displacement Mode Advanced Segment Processing
Combines a base register (BX/BP), an index register (SI/DI), and a fixed numeric variance displacement block. This compound calculation is standard layout practice for iterating over dimensional matrices or structured database field buffers.
7. Advanced String Operations & Repeat Execution Prefixes
Hardware-accelerated blocks for rapid memory array copying, buffer comparison, and string indexing.
8086 string operations automatically utilize preset registers as implicit operands: the Source Index (SI) registers map the input string bound to the Data Segment (DS), and the Destination Index (DI) maps the output track inside the Extra Segment (ES).
| Instruction | Syntax / Variant | Functional Operation Description | Pointer Shift |
|---|---|---|---|
| MOVSB / MOVSW | MOVSB (Byte) MOVSW (Word) |
Copies the byte or word located at DS:SI straight into the destination address container at ES:DI. Ideal for high-speed block data migrations. |
SI/DI ±1 (Byte) SI/DI ±2 (Word) |
| LODSB / LODSW | LODSB LODSW |
Loads the string element target from DS:SI straight up into the central Accumulator register (AL for byte setups, AX for word strings). |
SI ±1 or ±2 |
| STOSB / STOSW | STOSB STOSW |
Writes the contents of the AL/AX register directly into the target segment layout at ES:DI. This operation is standard code practice for initializing data array buffers. |
DI ±1 or ±2 |
| REP | REP MOVSB | Repeat Prefix. Instructs the CPU hardware to execute the string line iteratively. Automatically decrements the CX register after each loop pass until CX = 0. |
Controlled by CX |
CLD (Clear Direction Flag, setting DF=0) to force forward incrementing index pipelines, or STD (Set Direction Flag, setting DF=1) to force backward processing models.
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